Starting from the 45 nm CMOS IC process, as the feature size of the device increasingly shrinks, in order to suppress the short channel effect, the equivalent oxide thickness (EOT) of the gate dielectric layer must be reduced synchronously. Then, the ultra-thin conventional oxide or nitride oxide layer leads to a serious gate leakage. Therefore, the traditional poly-Si/SiON system is no longer applicable.
The appearance of a high-K gate dielectric layer effectively improves the gate leakage phenomenon of the device. However, poly-Si and high-K are combined to generate Fermi level pinning effect, which is not suitable for the threshold regulation of the MOS device. Therefore, poly-Si gates are gradually being replaced by metal gates.
For different MOS devices (i.e., PMOS devices and NMOS devices), metal gates having different work functions are required to regulate the threshold. There are many methods to form metal gates having different work functions, where the best method is to employ different metal materials to form a gate, i.e., NMOS requires a conduction band metal and PMOS requires a valence band metal. Although this method is optimal, a variety of different metal gate materials and complex integration processes are required. And the regulation scope is quite limited by employing a single metal post-process regulation method.
Therefore, the current most common method used to form a metal having different work functions is: first, as shown in FIG. 1(a), a first dummy gate stack and a second dummy gate stack, source/drain junction extensions 12a, 12b, and source/drain regions 13a, 13b are formed on the substrate 100, wherein each of the first dummy gate stack and the second dummy gate stack at least comprises a dummy gate 21a, 21b, the first dummy gate stack is used to form a gate of a first type device, and the second dummy gate stack is used to form a gate of a second type device; then, as shown in FIG. 1(b), a contact etch stop layer 30 and a first interlayer dielectric layer 40 are formed on the entire semiconductor structure; then, as shown in FIG. 1(c), part of the first interlayer dielectric layer 40 and part of the contact etch stop layer 30 are removed to expose the dummy gates 21a, 21b, and the dummy gates 21a, 21b are removed to form correspondingly a first gate trench 40a and a second gate trench 40b; then, as shown in FIG. 1(d), a first type metal layer work function modulation layer 41 is formed in the first gate trench 40a and the second gate trench 40b; then, as shown in FIG. 1(e), the first type metal layer work function modulation layer 41 located in the first gate trench 40a is removed; then, as shown in FIG. 1(f), the second type metal layer work function modulation layer 42 is deposited in the first gate trench 40a and the second gate trench 40b; then, as shown in FIGS. 1(g) and 1(h), the first gate trench 40a and the second gate trench 40b are filled with the metal material 43 to form a first gate 43a and a second gate 43b after implementing flattening operation, respectively; and finally, as shown in FIG. 1(i), in accordance with a conventional process step, a cap layer 50, a second interlayer dielectric layer 60 and a contact plug 70 are formed.
However, the above method still contains certain deficiencies:    (1) Since different CMOS devices are corresponding to metal materials with different work functions, in the CMOS integration process, it is required to deposit the first type metal layer work function modulation layer in the entire device region and then perform selective corrosion to remove the first type metal layer work function modulation layer located in the second type device region. However, selective corrosion is likely to cause damage to high-K materials on the surface of the second type device. The addition of an etch stop layer may prevent damage to high-K materials, but may correspondingly result in increase of the process complexity and undermine the ability of the metal gate work function to modulate the device threshold.    (2) The post-deposited second type metal layer deposition work function modulation layer, which is deposited simultaneously on the first type device, has some negative impacts on the threshold modulation of the first type device.
Therefore, it is desired to provide a dual metal gate CMOS device and its manufacturing method to overcome the above deficiencies.